The Parallel Decoding Architecture of Multi-Format VLD
Establishment and focus: In this paper, we propose an efficient architecture of MF-VLD (Multi-Format Variable Length Decoder), which is capable of variable length decoding and inverse quantization of various codec standards. The proposed MF-VLD is designed to be suitable for MPSOC (Multiprocessor System on Chip), and the bandwidth of AHB bus is reduced by applying bit-plane algorithm to inverse quantized data. It supports H.264, MPEG-2, MPEG-4, AVS, and VC-1 codec standards.
System: Parallel Decoding method using multi-processor is verified using INEXT board, which is emulation board with Xilinx Vertex5 XC4VL330 FPGA. The designed MF-VLD operates at 200 MHz in a 0.18 μm process and is approximately 620 K gates in size. The memory used is about 27 K bytes. In order to reduce the chip size, each variable-length decoding modules are arranged independently without combining, so that it is easy to add and remove according to the market situation later, and the design and verification shorten the time.