Random numbers are fundamental resources in the field of computing and engineering. They have a wide scope of application including cryptography and simulation. True Random Number Generators (TRNGs) are considered to be the most secure based on the quality of its entropy sources. With the availability of several sources of entropy, ring oscillator architecture can easily be used as a quality source of entropy for a TRNG due to the inherent jitters and the simplicity of its design. Since there is still a possibility of a generator to generate random numbers that do not meet the required security metrics, hence, it is imperative for a TRNG to be able to quickly regenerate another set of random bit sequence. For these reasons, this research, proposes a high-speed array-sampling and a post-processing unit ring oscillator-based TRNG with improved statistical measures and throughput for securing FPGA devices. The core architecture consists of digital primitive cells – the ring oscillator, Q-Flip Flop, and the CubeHash algorithm. These are used as the building blocks for constructing the proposed TRNG architecture.  This proposed hardware architecture reveals an improvement in throughput and the statistical measure of the quality of generated bits. The architecture was modeled and simulated using Verilog HDL, Modelsim SE, and Xilinx’s ISim simulation tools. This architecture was designed using both the Xilinx ISE and Vivado tools. The proposed design was implemented on the Spartan 6 and Cyclone IV FPGA devices and occupies an area of 3287 LUTs and 1714 Slice registers and had a maximum throughput of 1422 Mbps. Sampled bitstreams’ statistical accuracies were ascertained using NIST’s statistical Test package program.