Effect of bridging defect and the weak resistive open defect is a plunge key in the area of research. In these smart gadgets and devices world using VDSM technology, it is of utmost importance to analyze the effect of resistive open defects in on-chip cache memory since it occupies the largest part of complex systems and devices. Technology enhancements lead to an increase in distresses with the normal operation of the system due to process variation and temperature. Sensing weak resistive open defect and bridging defect in the on-chip cache memory is needed for the reliable operation of the circuit. This paper estimates the effectiveness of the proposed pre-discharged feeble cell detection (PDFCD) technique used to detect bridging faults and weak resistive open defects in on-chip cache memory. The fault detection capabilities analyzed for a large range of resistive values at random locations in memory. The implementation of the proposed method gives a minimum area overhead of 3.87% and less time penalty of 20.48µs for 1KB of memory.