Performance Analysis of Combinatorial Circuits Using Complementary and Pseudo NMOS Logic
This paper describes area optimized combinational circuit design using complex logic structures. Domino and Dynamic CMOS logic circuits are imperative as it offers has reduced latency and lesser number of transistor requirements as compared to conventional complementary CMOS based logic circuits. The pseudo NMOS logic-based circuit proposed methodology yields less dynamic power consumption and less gate count, compared to the static CMOS circuit. Tribulations allied with Pseudo NMOS logic like it slows rise time and static power dissipation. The results show the comparison of combinational circuits like multiplexer designed in complementary, pseudo NMOS and Dynamic CMOS Logic in terms of area. Circuit Implementation of the combinational circuit has been done in DSCH 2.0 and layout part is implemented in Microwind EDA tools using CMOS 250nm Technology file.