A Competent Multiplier Architecture with Reduced Transistor Count for Radix -2 Butterfly Computation of Fast Fourier Transform
Multiplication is the elementary process for computing the butterfly in Fast Fourier Transform. A formal multiplication task requires an extensively additonal hardware means and processing time in multiplication operation to a certain degree more than in addition and subtraction. In this work, architecture for multiplier is proposed which requires less space and works faster comparatively with other basic multiplier structures. The “UrdhvaTiryakbhyam” scheme offered by Vedic Mathematics is utilized to speed up the multiplication process. In addition, the reduction in transistor count is achieved by substrate biasing. Further the architecture is simulated in ORCAD software to analyse the area requirements of the Butterfly structure for computing Fast Fourier Transforms. The simulated results show that there is considerable reduction in transistor count and operating speed which makes the proposed multiplier a competent one with the standard multiplier architecture.