Designing High Speed 64 bit Multiplier using Vedic Sutra
Vedic multiplier is a unique and prompt multiplier dependent on Vedic mathematics. The main component used in this procedure is adder. Vedic multiplier’s performance can be enhanced by using fast adder. Hence in this paper we are using 64*64 bit multiplier using 32-bit Vedic multiplier and getting path delay lowest. For finding value of 64-bit multiplier, we need 32-bit multiplier for multiplication. Here we are applying Vedic Mathematics Sutra called “URDHVA TIRYAKABHYAM” for proposed 64*64 bit multiplier in Xilinx ISE 14.7. This design does not take more time for execution of the operation than comparison with available multiplier. This Vedic method is effective to improve the speed of image processing and digital signal processing. It works on high speed with great performance. This technique includes different types of wide area of image and digital signal processing. At the end, the result of proffered multiplier is compared with 64-bit multiplier using different adders.