Efficient Power Reduction Scheme for AES using Hardware-Software Co-Design
Embedded product design is driven by various design constraints like Device surface area utilization, volume, power consumption, and performance. These designs may even need to concurrently address the hardware and software requirements to bring out the product features at each stage while factoring in that, these requirements may additionally constrain or contribute to each other. All of these ought to be accomplished preserving in context time to Market and the Market timing. Hardware/Software Co-design methodology is an frequently employed way to deal to design embedded systems to reduce product development time and power consumption. Co-design offers the adaptability of design, as there are numerous Soft-core processors and Hardware development platforms that are offered in the market. This paper proposes a new Hardware/Software Co-design methodology, which has been used for enforcing the Advanced Encryption Standard (AES) algorithm for encrypting and decrypting 128,198 and 256 bits of data using NIOS II processor, from ALTERA to be imposed in FPGA retaining pace, area, and thermal dissipation as the focal point.