Implementation of Modified Low Power CMOS XOR Logic Gate using Reversible Logic
In modern VLSI technique, most of the adder design faces problems in four basic constraints namely power, chip area, speed and error occurrence, a modified hybrid VLSI adder 4T transistor design which integrates the logic of both Pseudo-NMOS and XOR Gate is proposed which is used to overcome the issues of accuracy, low speed and power consumption. This paper proposes a new design for 5-transistor CMOS-XOR gate which utilize less silicon area and consumes relatively lesser power than that of the existing 6-transistor and 12-transistor XOR gate designs and more accurate/good at output values when compared with the 4 and 3-transistor logics. The proposed XOR is used in full adders using Reversible gate Logic and its performance can be compared with the existing adders like conventional adder,Ripple carry Adder and Carry select Adder.This type of adders can be applied in the field of digital image processing and signal processing where importance is given to accuracy. The design will be implemented and simulated using CADENCE tool and performance will be tested. The proposed 5T full adder system using XOR logic has an accuracy of 99.988% and power consumption has reduced by more than 75%. Implementation of the 5T transistor adder using xor logic is done using the backend tool (CADENCE).